Semiconductor device

  • Inventors: NITTA HIDETO
  • Assignees: Nec Corp
  • Publication Date: November 02, 1988
  • Publication Number: JP-S63266855-A

Abstract

PURPOSE: To reduce a warpage to be generated during a wire bonding operation, a transfer molding operation or the like of a hybrid integrated circuit of compact structure by a method wherein a second insulating substrate whose coefficient of thermal expansion is close to the coefficient of thermal expansion of a first insulating substrate is provided at the lower part of a lead frame. CONSTITUTION: A hybrid integrated circuit is equipped with a printedcircuit board 4 having an insulating substrate 2 and a wiring conductor 3 and with an IC chip 5 on a lead frame 1. The IC chip 5, the wiring conductor 3 and the lead frame 1 are connected at prescribed positions by a wire bonding technique, and are plasticsealed by a transfer molding technique. In this integrated circuit, an insulating substrate 7 for preventing a curvature is provided at the lower part of the lead frame 1. For this insulating substrate 7 a ceramic insulating substrate whose coefficient of thermal expansion is close to the coefficient of thermal expansion of the insulating substrate 2 is to be used. Because the first and the second insulating substrates whose coefficient of thermal expansion is close to each other are provided on both sides of the lead frame in this manner, the warpage is never caused even when a temperature is changed. COPYRIGHT: (C)1988,JPO&Japio

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