PURPOSE: To speed up the charging and to reduce the current consumption by using a transistor (TR) so as to disconnect an output node of two output buffers from another node N 2 .
CONSTITUTION: A clock ϕ 1 and a buffer output N 1 are ANDed, a prescribed delay is given to three-stage of inverters to generate a clock ϕ 2 2. A clock ϕ 3 is generated from the clock ϕ 2 via two-stage inverters and a clock ϕ 4 is generated further via two-stage inverters, a clock ϕ 5 is generated from three-stage inverters from AND between the clock ϕ 2 and a buffer output N 2 and clocks ϕ 6 , ϕ 7 are generated from the clock ϕ 5 . In changing the input A from a high level to a low level in a circuit boosting the level of the clocks ϕ 1 , ϕ 2 and ϕ 5 to a power voltage or over, the output B reaches a voltage over a power supply Vcc therethrough from a low level. Further, it is required that the clocks ϕ 1 , ϕ 2 and ϕ 5 do not go to a high level at the same time.