Data processor

  • Inventors: ONO MASAHIRO
  • Assignees: Nec Corp
  • Publication Date: October 14, 1988
  • Publication Number: JP-S63247832-A

Abstract

PURPOSE: To shorten the executing time of an instruction requiring a memory access by storing previously the sums of the contents of plural registers to be used as addresses in a memory access state in terms of all combinations. CONSTITUTION: The sums of contents of base registers B1WB7 of a base register group 12 and the contents of index registers R1WR3 of an index register group 3 are used as addresses for memory accesses. In this case, the addresses are combined in 21 different ways. Thus these 21 ways of combination are previously calculated by an adder 14 and held by an address register 15. When a machine word instruction requiring a memory access is carried out, the sum of the contents of designated two registers is read out of the register 15 based on the base and index parts of the machine word instruction held by a register 11. Thus the time is not required for calculation of an address and the instruction executing time is shortened. COPYRIGHT: (C)1988,JPO&Japio

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